1. Field of the Invention
The invention relates generally to flash memory devices and more particularly to a method of fabricating flash memory devices having an ONO layer which contains a silicon nitride layer sandwiched between two silicon oxide layers.
2. Description of the Related Art
A flash memory having an ONO layer is illustrated in FIG. 1. It includes an ONO layer 60 disposed on top of a silicon substrate 10, and a control gate 71, typically of polysilicon, disposed on top of the ONO layer 60. The ONO layer 60 comprises a lower layer 61 made of silicon oxide, a middle layer 62 made of silicon nitride, and an upper layer 63 made of silicon oxide.
FIGS. 2A-2J illustrate the conventional process for fabricating a flash memory device having an ONO layer. First, a silicon oxide layer 20 is thermally grown on the silicon substrate 10 to form the structure of FIG. 2A. Then, as shown in FIG. 2B, nitrogen atoms (N or N2) are implanted at normal energy levels (greater than or equal to 10 keV) into the silicon oxide layer 20. The nitrogen implanting step is followed by heating to anneal out the implant damage and to diffuse the implanted nitrogen to the Si/SiO2 interface 21 and cause SiN bonds to be formed at the Si/SiO2 interface 21.
Subsequently, a silicon nitride layer 30 is deposited on top of the silicon oxide layer 20 by chemical vapor deposition (CVD). FIG. 2C shows the silicon nitride layer 30 deposited on top of the silicon oxide layer 20. A second layer of silicon oxide 40 is then formed on top of the silicon nitride layer 30 and the resulting structure is shown in FIG. 2D. Thereafter, as shown in FIG. 2E, a photoresist 50 is formed on top of the second silicon oxide layer 40, and this semiconductor structure is etched until an upper surface of the silicon substrate 10 is exposed. The resulting structure, shown in FIG. 2F, is subsequently implanted with arsenic and boron ions using the remaining photoresist 50 as a mask and heated to diffuse the implanted ions.
The remaining photoresist 50 is stripped away and, as shown in FIG. 2G, a polysilicon layer 70 is deposited on top of the exposed surface of the silicon substrate 10 and on top and sidewalls of the ONO layer 60. The polysilicon layer 70 is then patterned using conventional lithography techniques and a control gate 71 remains on top of the ONO layer 60. FIG. 2H shows the resulting gate structure 75 including the control gate 71 and the ONO layer 60.
Oxide spacers 81, 82, shown in FIG. 2J, are formed on the sidewalls of the gate structure 75 by (i) depositing a conformal layer of silicon oxide 80 by CVD on the exposed surface of the silicon substrate 10 and on top and sidewalls of the gate structure 75 (FIG. 2I), and (ii) anisotropically etching the deposited silicon oxide.
The invention provides a process for forming an ONO flash memory device using low energy nitrogen implantation that reduces the damage to the underlying silicon substrate during implantation.
The invention produces a gate structure for an ONO flash memory device that includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted into the first layer of silicon oxide at less than normal energy levels to reduce the amount of damage to the underlying semiconductor substrate. After low energy nitrogen implantation, the semiconductor structure is heated to anneal out the implant damage and to diffuse the implanted nitrogen to the substrate and silicon oxide interface to cause SiN bonds to be formed at that interface. The SiN bonds is desirable because they improve the bonding strength at the interface and the nitrogen remaining in the silicon oxide layer increases the oxide bulk reliability.
Additional objects, features and advantages of the invention will be set forth in the description of preferred embodiments which follows.